Device-scaling constraints imposed by the van der Waals gap formed in two-dimensional materials

• 成果类型: Article
• 署名作者: Pourfath, Mahdi; Grasser, Tibor
• 署名单位: Technische Universitat Wien
• 刊物名称: SCIENCE
• ISSN/ISSBN: 0036-8075; 1095-9203
• DOI: 10.1126/science.aeb2271
• 发表日期: 2026-05-21
• 页码: eaeb2271
• 关键词: initio molecular-dynamics; GATE DIELECTRICS; boron-nitride; insulator; radii

摘要

Transistor miniaturization requires controlling gate leakage through ultrathin dielectrics and minimizing source-drain contact resistance. Although two-dimensional semiconductors offer excellent electrostatic control, their interfaces with gate dielectrics and contact metals often form a van der Waals (vdW) gap that affects device performance and acts as a tunneling barrier with a low dielectric constant. While this reduces dielectric leakage, it increases metal-channel contact resistance and introduces a parasitic series capacitance to the gate. We quantified the trade-off between leakage suppression and electrostatic and contact-resistance scaling limits. As a result of this trade-off, many insulators fail to meet scaling targets, and metal-channel contacts fall short of required resistances. Zipper-like interfaces, where quasi-covalent bonding removes the vdW gap without creating dangling bonds, offer a path toward ultrascaled transistor designs.