Addressing interconnect challenges for enhanced computing performance

• 成果类型: Review
• 署名作者: Kim, Joon-Seok; Kim, Joonyun; Yang, Dae-Jin; Shim, Jaewoo; Hu, Luhing; Lee, Chang-Seok; Kim, Jeehwan; Kim, Sang Won
• 署名单位: Samsung; Massachusetts Institute of Technology (MIT); Massachusetts Institute of Technology (MIT); Massachusetts Institute of Technology (MIT); Hongik University
• 刊物名称: SCIENCE
• ISSN/ISSBN: 0036-13404
• DOI: 10.1126/science.adk6189
• 发表日期: 2024-12-01
• 关键词: diffusion barrier; dram; resistance; cu; ru; integration; monolayer; capacitor; graphene; memory

摘要

The advancement in semiconductor technology through the integration of more devices on a chip has reached a point where device scaling alone is no longer an efficient way to improve the device performance. One issue lies in the interconnects connecting the transistors, in which the resistivity of metals increases exponentially as their dimensions are scaled down to match those of the transistors. As a result, the total signal processing delay is dominated by the resistance-capacitance (RC) delay from the interconnects rather than the delay from the transistors' switching speed. This bottleneck has spurred efforts both in academia and industry to explore alternative materials and disruptive device structures. Therefore, we suggest strategies to overcome the RC delay of the interconnects in both material and device aspects.