Van der Waals polarity-engineered 3D integration of 2D complementary logic

• 成果类型: Article
• 署名作者: Guo, Yimeng; Li, Jiangxu; Zhan, Xuepeng; Wang, Chunwen; Li, Min; Zhang, Biao; Wang, Zirui; Liu, Yueyang; Yang, Kaining; Wang, Hai; Li, Wanying; Gu, Pingfan; Luo, Zhaoping; Liu, Yingjia; Liu, Peitao; Chen, Bo; Watanabe, Kenji; Taniguchi, Takashi; Chen, Xing-Qiu; Qin, Chengbing; Chen, Jiezhi; Sun, Dongming; Zhang, Jing; Wang, Runsheng; Liu, Jianpeng; Ye, Yu; Li, Xiuyan; Hou, Yanglong; Zhou, Wu; Wang, Hanwen; Han, Zheng
• 署名单位: Chinese Academy of Sciences; Institute of Metal Research, CAS; Chinese Academy of Sciences; University of Science & Technology of China, CAS; Shandong University; Chinese Academy of Sciences; University of Chinese Academy of Sciences, CAS; Chinese Academy of Sciences; University of Chinese Academy of Sciences, CAS; ShanghaiTech University; ShanghaiTech University; Sun Yat Sen University; Peking University; Peking University; Chinese Academy of Sciences; Shanxi University; State Key Laboratory of Quantum Optics & Quantum Optics Devices; Shanxi University; Peking University; Tsinghua University; Collaborative Innovation Center of Quantum Matter; Peking University; National Institute for Materials Science; National Institute for Materials Science; State Key Laboratory of Quantum Optics & Quantum Optics Devices; Shanxi University; Liaoning Academy Materials
• 刊物名称: Nature
• ISSN/ISSBN: 0028-5806
• DOI: 10.1038/s41586-024-07438-5
• 发表日期: 2024-06-13
• 页码: 346-+
• 关键词: total-energy calculations; 2-dimensional materials; mos2; wse2; transistors; resistance; devices; scale

摘要

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis(1-3). Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures(4,5), as well as hetero-2D layers with different carrier types(6-8), have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9-17) and MoS2 (refs. 11,18-28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm(2) V-1 s(-1), on/off ratios reaching 10(6) and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.