An integrated large-scale photonic accelerator with ultralow latency

• 成果类型: Article
• 署名作者: Hua, Shiyue; Divita, Erwan; Yu, Shanshan; Peng, Bo; Roques-Carmes, Charles; Su, Zhan; Chen, Zhang; Bai, Yanfei; Zou, Jinghui; Zhu, Yunpeng; Xu, Yelong; Lu, Cheng-kuan; Di, Yuemiao; Chen, Hui; Jiang, Lushan; Wang, Lijie; Ou, Longwu; Zhang, Chaohong; Chen, Junjie; Zhang, Wen; Zhu, Hongyan; Kuang, Weijun; Wang, Long; Meng, Huaiyu; Steinman, Maurice; Shen, Yichen
• 署名单位: Stanford University
• 刊物名称: Nature
• ISSN/ISSBN: 0028-1695
• DOI: 10.1038/s41586-025-08786-6
• 发表日期: 2025-04-10
• 关键词: NETWORKS; chip

摘要

Integrated photonics, particularly silicon photonics, have emerged as cutting-edge technology driven by promising applications such as short-reach communications, autonomous driving, biosensing and photonic computing1, 2, 3-4. As advances in AI lead to growing computing demands, photonic computing has gained considerable attention as an appealing candidate. Nonetheless, there are substantial technical challenges in the scaling up of integrated photonics systems to realize these advantages, such as ensuring consistent performance gains in upscaled integrated device clusters, establishing standard designs and verification processes for complex circuits, as well as packaging large-scale systems. These obstacles arise primarily because of the relative immaturity of integrated photonics manufacturing and the scarcity of advanced packaging solutions involving photonics. Here we report a large-scale integrated photonic accelerator comprising more than 16,000 photonic components. The accelerator is designed to deliver standard linear matrix multiply-accumulate (MAC) functions, enabling computing with high speed up to 1 GHz frequency and low latency as small as 3 ns per cycle. Logic, memory and control functions that support photonic matrix MAC operations were designed into a cointegrated electronics chip. To seamlessly integrate the electronics and photonics chips at the commercial scale, we have made use of an innovative 2.5D hybrid advanced packaging approach. Through the development of this accelerator system, we demonstrate an ultralow computation latency for heuristic solvers of computationally hard Ising problems whose performance greatly relies on the computing latency.