Spin-qubit control with a milli-kelvin CMOS chip

• 成果类型: Article
• 署名作者: Bartee, Samuel K.; Gilbert, Will; Zuo, Kun; Das, Kushal; Tanttu, Tuomo; Yang, Chih Hwan; Stuyck, Nard Dumoulin; Pauka, Sebastian J.; Su, Rocky Y.; Lim, Wee Han; Serrano, Santiago; Escott, Christopher C.; Hudson, Fay E.; Itoh, Kohei M.; Laucht, Arne; Dzurak, Andrew S.; Reilly, David J.
• 署名单位: University of Queensland; University of Sydney; University of New South Wales Sydney; Keio University
• 刊物名称: Nature
• ISSN/ISSBN: 0028-2823
• DOI: 10.1038/s41586-025-09157-x
• 发表日期: 2025-07-10
• 关键词: quantum processor; silicon

摘要

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction1, 2-3. However, with each physical qubit needing multiple control lines, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware4, 5-6. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired up by miniaturized interconnects7, 8, 9-10. Even so, heat and crosstalk from closely integrated control have the potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise11,12. Here we benchmark silicon metal-oxide-semiconductor (MOS)-style electron spin qubits controlled by heterogeneously integrated cryo-complementary metal-oxide-semiconductor (cryo-CMOS) circuits with a power density sufficiently low to enable scale-up. Demonstrating that cryo-CMOS can efficiently perform universal logic operations for spin qubits, we go on to show that milli-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our sub-kelvin CMOS platform, with about 100,000 transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a 'chiplet-style' control architecture.